The present invention generally relates to instructions used in sequential programming languages, and more particularly to instructions that include information regarding parallel execution relationships.
The demand for increased realism in computer graphics for games and other applications has been steady for some time now and shows no signs of abating. This has placed stringent performance requirements on computer system components, particularly graphics processing units. For example, to generate improved images, an ever increasing amount of data needs to be processed by a graphics processing unit. In fact, so much graphics data now needs to be processed that conventional processing techniques are not up to the task and need to be replaced.
Fortunately, the engineers at NVIDIA Corporation in Santa Clara, Calif. have developed a new type of processing circuit that is capable of meeting these incredible demands. This amazing new circuit is based on the concept of multiple single-instruction multiple-data processors.
These new processors have such an extensive capacity, allowing them to execute so many processes at the same time, that it has become difficult to keep them fully occupied. In particular, it is now desirable to be able to concurrently execute multiple tasks, that is, to execute two or more tasks at the same time, instead of waiting for one to complete then starting the next.
This graphics data is typically processed under the control of commands or instructions in a programming language such as C or C++. These languages are serial in nature, that is, an instruction to perform a first task is followed by an instruction to perform a second task. This makes it difficult to inform these newly developed processors that two or more processes can be executed in parallel.
Accordingly, what is needed are circuits, methods, and apparatus that allow parallel execution relationships to be expressed in commands or instructions in a sequential programming language.